Design Technology Co-Optimization for Gate-All-Around Nanosheet Transistors Considering Source/Drain Confinement and Post- Gate Single Diffusion Break

发表于 2026-8-9 20:51:57

期刊：IEEE Transactions on Electron Devices

文献作者：Dawei Wang; Tao Liu; Xin Sun; Ziqiang Huang; Lewen Qian; Xinlong Guo; Liming Wang; Min Xu; David Wei Zhang

出版日期：2024-7-

DOI号：10.1109/ted.2024.3403794

下载链接：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=10540029

文献链接：https://doi.org/10.1109/ted.2024.3403794

当前文献来源于 Institute of Electrical and Electronics Engineers (IEEE)。

备注信息：

发表于 2026-8-9 20:51:58

: 当前求助已完成，请重新发起求助。
已完结状态的附件将会在24小时内删除。

[IEEE] Design Technology Co-Optimization for Gate-All-Around Nanosheet Transistors Considering Source/Drain Confinement and Post- Gate Single Diffusion Break

已采纳

同分类求助

最新回复

站点公告

今日热心研友

（热心研友QQ群）

[IEEE] Design Technology Co-Optimization for Gate-All-Around Nanosheet Transistors Considering Source/Drain Confinement and Post- Gate Single Diffusion Break 一键复制