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[IEEE] Highly Stackable 3D DRAM of Dual-Gate IGZO 2T0C with Record 3 Bits/Cell and 400s Data Retention

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期刊：2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

文献作者：Fuxi Liao; Zhengyong Zhu; Guanhua Yang; Xuanming Zhang; Menggan Liu; Kaifei Chen; Wendong Lu; Zihan Li; Naide Mao; Bok-Moon Kang; Jinghong Shi; Meichen Jin; Chang Liu; Jing Liang; Gui-Lei Wang; Congyan Lu; Jinshan Yue; Lingfei Wang; Jiawei Wang; Di Geng; Nianduan Lu; Chao Zhao; Arokia Nathan; Ling Li; Ming Liu

出版日期：2026-6-14

DOI号：10.1109/vlsitechnologyandcir65830.2026.11577586

下载链接：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=11577586

文献链接：https://doi.org/10.1109/vlsitechnologyandcir65830.2026.11577586

当前文献来源于 IEEE。

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[IEEE] Highly Stackable 3D DRAM of Dual-Gate IGZO 2T0C with Record 3 Bits/Cell and 400s Data Retention