A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement

发表于昨天 13:33

期刊：2023 IEEE International Solid- State Circuits Conference (ISSCC)

文献作者：Woongrae Kim; Chulmoon Jung; Seongnyuh Yoo; Duckhwa Hong; Jeongjin Hwang; Jungmin Yoon; Ohyong Jung; Joonwoo Choi; Sanga Hyun; Mankeun Kang; Sangho Lee; Dohong Kim; Sanghyun Ku; Donhyun Choi; Nogeun Joo; Sangwoo Yoon; Junseok Noh; Byeongyong Go; Cheolhoe Kim; Sunil Hwang; Mihyun Hwang; Seol-Min Yi; Hyungmin Kim; Sanghyuk Heo; Yeonsu Jang; Kyoungchul Jang; Shinho Chu; Yoonna Oh; Kwidong Kim; Junghyun Kim; Soohwan Kim; Jeongtae Hwang; Sangil Park; Junphyo Lee; Inchul Jeong; Joohwan Cho; Jonghwan Kim

出版日期：2023-2-19

DOI号：10.1109/isscc42615.2023.10067805

下载链接：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=10067805

文献链接：https://doi.org/10.1109/isscc42615.2023.10067805

当前文献来源于 IEEE。

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发表于昨天 13:39

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[IEEE] A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement

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[IEEE] A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement